Abstract: This paper presents the design of high performance Vedic multiplier using compressors. The three major trepidations of designing digital circuits are area, speed and power. With advancing technology, encumbrance is being laid on attaining high speed, low power and less area. Multiplier is designed based on Vedic mathematics which has enhanced the performance of the circuit. In this paper, a new technique is introduced for 4:2 compressor and 5:2 compressor to mend the performance of the multiplier. The conventional circuits include designing with XOR modules which has improved performance over the full adders. In this paper, the compressor is designed using multiplexers which have shown advanced performance over the existing techniques. The design is implemented using Cadence EDA tools and area and timing have been calculated. The proposed technique has obtained 8.4 % reduction in area and 27.7 % improvement in PDP compared to the previous technique.

Keywords: Vedic, Compressor, Multiplexer